With the rapid adoption of generative AI, AI data centers are seeing continued increases in the speed and capacity of server-to-server communications. Optical communication is also evolving from 800G to 1.6T and toward next-generation technologies. As data rates increase, higher-quality reference clocks are required for DSPs and SerDes. 

When selecting a timing device, price, size, and headline jitter figures alone are not enough to determine whether a device is suitable for a particular system. For operation at 625 MHz, it is important to evaluate jitter and phase noise at the actual operating frequency, as well as the measurement bandwidth, specification limits such as typical and maximum values, temperature and power-supply conditions, and the clock-generation architecture. 

Rather than simply comparing crystal oscillators with MEMS oscillators, this article explains the key factors to consider when selecting timing devices for AI data centers and 1.6T high-speed optical communications.

The Growing Importance of Clock Quality as AI Data Centers Increase in Speed

As AI data centers become faster, reference clock quality is becoming an increasingly important consideration in system design. GPU servers supporting generative AI workloads are handling ever-growing volumes of data, while the optical links connecting servers are advancing from 800G to 1.6T. 

As data rates increase, each UI (Unit Interval)—the time allotted to one symbol—becomes shorter, leaving less timing margin for signals to be correctly interpreted. Jitter and noise in the clock can affect factors such as eye opening and BER (bit error rate), making it essential to carefully evaluate the quality of the clocks supplied to DSPs and SerDes. 

In addition, optical transceivers, which integrate components at high densities, face design constraints related to heat generation, power consumption, and PCB area. When selecting a timing device, it is therefore important to consider not only clock performance but also its impact on the system as a whole.

Comparing Crystal and MEMS Oscillators Under the Same Operating Conditions

Because crystal and MEMS oscillators differ in their oscillation mechanisms and product designs, neither technology can be considered universally superior based on the underlying technology alone. Depending on the product, MEMS oscillators may offer advantages such as compact size and shock resistance, while some crystal oscillators excel in high-frequency and low-jitter performance. 

The key is to compare devices under the same actual operating frequency, measurement conditions, and system configuration. For high-speed optical communication applications at 625 MHz in particular, it is important to consider not only the conditions under which jitter is measured, but also cost and power consumption at the overall system level rather than evaluating the oscillator in isolation.

Evaluating Jitter Under Actual Operating Conditions

When comparing the jitter performance of timing devices, it is important to review measurement results obtained under conditions that closely reflect the actual application. Jitter values can vary depending not only on the measurement frequency, but also on factors such as measurement bandwidth, supply voltage, and temperature. 

For example, when a system requires a 625 MHz clock, comparing only jitter values measured at 156.25 MHz does not guarantee that the same performance will be achieved at 625 MHz. Even at the same frequency, a direct comparison can be difficult if the measurement bandwidths differ. 

When reviewing a datasheet, it is therefore important to look beyond the jitter value itself and check the operating frequency, measurement bandwidth, supply voltage, and temperature conditions. Comparing products under equivalent real-world operating conditions makes it easier to determine which device is best suited to the intended application.

Evaluating Cost and Power Consumption at the System Level

The cost and power consumption of a timing device should be evaluated not only at the oscillator level, but across the entire circuit required to achieve the necessary clock quality. Depending on the oscillator, additional components or circuitry such as PLLs, frequency multipliers, and jitter cleaners may be required. 

Adding such circuitry can affect not only component costs, but also power consumption, heat generation, and PCB area. The potential increase in engineering effort required for circuit design and performance evaluation should also be taken into account. 

When comparing products, it is therefore important to look beyond the unit price and current consumption of the oscillator itself and consider the total cost, power consumption, and design effort associated with the complete solution, including any additional components.

Three Key Performance Parameters to Check for a 625 MHz Clock

When comparing clocks for 1.6T high-speed optical communications, it is important not to rely on a single specification, but to evaluate clock quality at 625 MHz using multiple performance parameters. In particular, phase jitter, phase noise, and spurious signals each provide insight into different aspects of clock instability and noise. 

The differences among these three parameters and the key points to check are summarized below.

Rather than assessing each parameter in isolation, it is important to evaluate them collectively while taking into account the actual operating conditions at 625 MHz and the clock-generation architecture.

Phase Jitter: Evaluating Timing Variations in the Clock

Phase jitter is a measure of how much the timing of a clock’s rising and falling edges deviates from their ideal positions. In high-speed communications, the time allocated to each signal is extremely short, so even small timing variations can reduce the available timing margin and potentially affect signal quality. 

When using a 625 MHz clock, it is important to check phase jitter values measured at the actual operating frequency of 625 MHz. Because jitter values also vary depending on the measurement bandwidth, both the measurement frequency and bandwidth should be taken into account when comparing products.

Phase Noise: Examining Noise Across the Frequency Spectrum

Phase noise indicates how fluctuations in a clock signal are distributed across different frequencies. While RMS phase jitter expresses the total amount of timing variation within a specified range as a single value, phase noise shows how much noise is present at different offset frequencies. 

For example, even products with similar RMS phase jitter values may have different phase-noise distributions across the frequency spectrum. To evaluate clock quality at 625 MHz in greater detail, it is therefore necessary to compare not only jitter values but also phase-noise characteristics. 

Examining these noise characteristics, which may not be apparent from a single headline specification, makes it easier to select a clock that is well suited to the intended application.

Spurious Signals: Examining Noise Components at Specific Frequencies

Spurious signals, or spurs, are unwanted discrete spectral components that appear at specific frequencies around the carrier. On a phase-noise plot, they can be identified as peaks that rise above the surrounding noise floor. 

Unlike noise distributed across a broad frequency range, spurs appear as distinct peaks at specific frequencies and are therefore an important consideration when evaluating clock quality. When PLLs, frequency multipliers, or digital compensation are used, it is also necessary to consider the possibility that the clock-generation architecture itself may introduce spurs. 

However, the presence of a peak alone is not sufficient to determine whether a product is suitable. For operation at 625 MHz, it is important to check the frequency and level of each spur and evaluate whether it falls within a range that could affect signal quality in the actual system.

Comparing Jitter Under Equivalent Measurement Conditions

Phase jitter cannot always be compared accurately simply by looking at the values listed in datasheets. Differences in measurement bandwidth, frequency, temperature, and power-supply conditions can affect both the measured values and how those values should be interpreted. 

When comparing timing devices, it is important to align the measurement conditions as closely as possible and evaluate both typical (Typ.) and maximum (Max.) values.

Comparing Jitter Using the Same Measurement Bandwidth

When comparing phase jitter, it is important to use the same measurement bandwidth. Phase jitter is calculated by integrating phase noise over a specified range of offset frequencies, so the resulting value varies depending on the frequency range used for the measurement. 

For example, a value calculated over a narrow bandwidth and one calculated over a wider bandwidth include different ranges of noise and therefore cannot be directly compared on the same basis. For River Eletec’s KCRO-05, the phase jitter measurement bandwidth at 625 MHz is specified as 12 kHz to 20 MHz. 

When selecting a timing device, be sure to check the measurement bandwidth as well as the jitter value and, wherever possible, compare products under equivalent measurement conditions.

Confirming Both Typical and Maximum Values

When evaluating the performance of a timing device, it is important to check not only the typical (Typ.) value but also the maximum (Max.) value. While the typical value provides a useful indication of representative product performance, it does not guarantee that every device will deliver the same level of performance. 

Particularly when designing for mass production, variations between individual devices must be taken into account to ensure that the required specifications can be consistently met. When a maximum value is specified, designers can assess the available design margin based on the expected upper limit. 

Rather than focusing solely on typical performance, it is important to evaluate both typical and maximum values to determine whether sufficient margin exists against the required specifications.

Evaluating Performance Under Equivalent Temperature and Power-Supply Conditions

Timing devices should be evaluated under conditions that reflect the actual operating environment. In optical transceivers for AI data centers, high-density component integration can result in elevated ambient temperatures, meaning that typical values obtained at room temperature may not provide a complete picture of performance under actual operating conditions. 

When selecting a product, it is important to check the expected operating temperature range and examine how jitter and phase-noise characteristics vary with temperature. Supply voltage and noise present on the power supply are also factors that can affect clock quality. 

Where possible, it is therefore important to evaluate how clock performance changes in the presence of power-supply noise. Looking beyond datasheet conditions and considering the actual power-supply design and operating environment helps ensure a stable clock supply.

Evaluating the Clock-Generation Architecture at the System Level

How the required frequency is generated is another important consideration when selecting a timing device. PLLs and frequency multipliers provide flexibility in frequency generation, but phase-noise and spurious characteristics can vary depending on the clock-generation path. 

Rather than evaluating the oscillator in isolation, it is important to consider any additional circuitry and assess the quality of the clock ultimately supplied to the DSPs and SerDes.

Considering the Clock-Generation Method, Not Just Frequency

When selecting a timing device, it is important to consider not only the supported frequencies but also how the required frequency is generated. A configuration that directly oscillates at the fundamental frequency of 625 MHz has a different clock-generation path from one that generates 625 MHz from a lower frequency using a PLL or frequency multiplier. 

With ideal frequency multiplication, the phase noise of the input signal increases by 20log₁₀N dB, where N is the multiplication factor. When a PLL is used, it is also essential to evaluate characteristics associated with the VCO (voltage-controlled oscillator), loop bandwidth, and other elements in addition to the reference clock. 

Taking the characteristics of each clock-generation method into account, jitter, phase noise, and spurious performance should be compared at 625 MHz.

Evaluating Clock Quality Including Additional Circuitry

When PLLs, jitter cleaners, filters, compensation circuits, or other components are used to achieve the required clock quality, it is important to evaluate the entire clock-generation path, including this additional circuitry. A properly designed PLL or jitter cleaner may reduce jitter and noise present in the input clock. 

Components within a PLL, including the VCO, PFD (phase-frequency detector), charge pump, and frequency dividers, can also influence the noise characteristics of the output clock. As additional circuitry is introduced, its impact on power consumption, heat generation, and PCB area must also be taken into account. 

Rather than relying solely on the specifications of the oscillator itself, it is important to evaluate the quality of the clock ultimately supplied to the DSPs and SerDes.

Evaluating Timing Devices for Power Consumption, Heat Generation, and PCB Integration

As AI data centers and optical transceivers move toward higher speeds and greater component densities, constraints related to power consumption, heat generation, and PCB space are becoming increasingly stringent. When selecting a timing device, it is therefore important to consider not only clock performance but also the entire circuit required to achieve the necessary clock quality. 

If additional circuitry is required, the comparison should take into account not only power consumption and heat generation, but also component count, PCB area, and the engineering effort required for design and implementation. 

Evaluating Power Consumption and Heat Generation Including Additional Circuitry

When comparing the power consumption of timing devices, it is important to evaluate the entire circuit required for clock generation rather than the oscillator alone. If PLLs, jitter cleaners, compensation circuits, or other components are added, the power they consume and the heat they generate also contribute to the overall system requirements. 

This is particularly important in high-density optical transceivers, where numerous components must be integrated into a limited space. Even small amounts of heat generated by individual components can accumulate and affect the overall thermal design. It is therefore necessary to determine how much power is consumed in delivering a 625 MHz clock at the required level of quality. 

Rather than considering only the current consumption of the oscillator itself, power consumption should be evaluated together with the heat generated by any additional circuitry.

Evaluating Component Count, PCB Area, and Design Effort

When selecting a timing device, it is important to consider not only the unit cost of the device but also the number of components, PCB area, and engineering effort required for clock generation. Adding PLLs, jitter cleaners, termination circuits, power-supply circuits, or other components increases both the space required on the PCB and the amount of routing. 

A higher component count can not only make power-supply and circuit design more complex but also increase the engineering effort required for functional verification and performance evaluation. In optical transceivers, where high-density integration is essential, the impact on PCB area also cannot be overlooked. 

Rather than comparing the price of the oscillator alone, it is important to assess the overall system burden, including implementation, design, and evaluation.

Choosing Between Crystal and MEMS Oscillators Based on the Application and Requirements

When selecting between crystal and MEMS oscillators, it is important not to determine which is superior based solely on the underlying technology, but to evaluate each option against the performance required for the intended application. As discussed above, each technology has its own characteristics, while performance and specifications can also vary between individual products based on the same technology. 

Different applications, such as IoT devices, automotive systems, and industrial equipment, have different performance requirements and priorities. Products should therefore be compared based on actual operating conditions and required specifications rather than on the oscillator technology alone. 

For AI data centers and 1.6T high-speed optical communications, key considerations include actual performance at 625 MHz, such as jitter, phase noise, and spurious characteristics, as well as temperature and power-supply conditions and the clock-generation architecture. If PLLs or other additional circuitry are required, power consumption, heat generation, and PCB area should also be taken into account to select the timing device best suited to the overall system.

KCRO-05: Direct Fundamental-Mode Oscillation at 625 MHz

For applications requiring an ultra-low-jitter 625 MHz clock, River Eletec’s KCRO-05 is a compelling option. Leveraging the company’s proprietary KoT cut® and OPAW® technologies, the KCRO-05 can oscillate directly at the 625 MHz fundamental frequency without using a PLL or frequency multiplier. 

The key specifications and features of the KCRO-05 are shown below.

By generating 625 MHz directly without a PLL, the KCRO-05 can help simplify circuitry and reduce component count in some systems. Where additional circuitry can be eliminated, this approach may also help reduce power consumption and heat generation, making the KCRO-05 a compelling option for 1.6T optical communications, where both high-density integration and high clock quality are essential.

Selecting Clocks with the Transition from 1.6T to 3.2T in Mind

Optical communications for AI data centers are expected to advance beyond 1.6T toward even higher speeds. When selecting a timing device, it is therefore important to consider not only current specifications but also future system requirements. 

When using a 625 MHz reference clock for 1.6T high-speed optical communications, factors such as jitter, phase noise, spurious characteristics, temperature characteristics, and the clock-generation architecture should be evaluated under actual operating conditions to determine whether sufficient performance margin exists relative to the system requirements. With direct fundamental-mode oscillation at 625 MHz and ultra-low-jitter performance, the KCRO-05 is one compelling option. 

In the 3.2T generation, the required clock frequencies and performance levels may change. Rather than assessing suitability for future generations based solely on current specifications, it is important to confirm the applicable standards and specific system requirements and comprehensively evaluate clock quality, ease of integration, power consumption, and heat generation.

Timing Device Selection Checklist for AI Data Centers

When selecting timing devices for AI data centers and 1.6T high-speed optical communications, it is important to compare more than headline specifications such as jitter. Measurement conditions, clock-generation architecture, power consumption, and ease of integration should also be taken into account. When selecting a product or reviewing a datasheet, consider the following points.

The key to selecting the right device is to avoid judging products solely on individual specification values and instead compare them under equivalent actual operating conditions. Rather than evaluating the oscillator in isolation, the entire system required to achieve the necessary clock quality should be considered as a whole.

Conclusion: Selecting the Optimal Clock Based on Actual 625 MHz Performance