With the widespread adoption of generative AI, AI data centers are rapidly transitioning from 800G to 1.6T-class communication speeds. As communication speeds continue to increase, the impact of phase jitter and phase noise on communication performance can no longer be overlooked.
In high-speed optical communication systems, PLLs (phase-locked loops) have long been widely used for high-frequency clock generation. However, as the industry moves toward 1.6T-class ultra-high-speed communication, demand for even lower-jitter clock solutions continues to grow.
One approach attracting increasing attention is PLL-free fundamental-mode oscillation, which directly generates high-frequency signals without relying on a PLL. This article examines the phase-jitter challenges of the 1.6T optical communication era, the technical characteristics of PLL-free fundamental-mode oscillation, and the advantages of River Eletec’s KCRO-05.
Clock Performance Becoming Increasingly Important as AI Data Centers Move to Higher Speeds
AI data centers are undergoing rapid upgrades in communication infrastructure as generative AI becomes more widely adopted. In particular, as the transition from 800G to 1.6T-class communication accelerates, the impact of phase jitter and phase noise on communication performance is becoming increasingly significant.
This section explains why ultra-low-jitter clocks are required in high-speed optical communication.
The Accelerating Shift From 800G to 1.6T Optical Communication
AI data centers are rapidly transitioning from 800G to 1.6T-class communication speeds. This shift is driven by the expansion of GPU clusters as generative AI becomes more widely used. As the amount of data required for training and inference increases, securing sufficient bandwidth for server-to-server communication has become a key factor affecting overall system performance.
In terms of communication standards, IEEE P802.3dj is developing next-generation optical transmission standards that enable 200 Gbps per lane. Development of next-generation optical transceivers such as OSFP-XD is also accelerating , while requirements for high-density integration and lower power consumption continue to increase.
As communication speeds rise, maintaining signal integrity becomes more difficult at the equipment design level. As a result, there is growing interest in the clock performance required for optical communication.
The AI server market is also expected to continue expanding, supporting these technology trends.
【AI Server Market Size Forecast, 2026–2030】
| 2026 | 2027 | 2028 | 2029 | 2030 | |
|---|---|---|---|---|---|
| Quantity, thousand units | 3,000 | 3,800 | 4,800 | 6,000 | 7,500 |
| Value, JPY million | 10,500,000 | 13,500,000 | 17,000,000 | 21,500,000 | 27,000,000 |
Source: 2026 Edition of the Survey on Electronic Devices Installed in AI Server-Related Equipment (In-house survey)
Market growth means increased demand not only for AI servers themselves, but also for peripheral devices such as optical transceivers, DSPs, and SerDes. As high-speed communication equipment becomes more widely deployed , the importance of clocks that ensure signal integrity will also increase.
Against this backdrop , requirements for ultra-low-jitter clocks are expected to become even more stringent.
In High-Speed Communication, Phase Jitter Can Directly Affect BER
In high-speed communication, phase jitter has a significant impact on BER (Bit Error Rate). This is because, as communication speeds increase, the time available to determine each bit becomes increasingly limited.
For example, as the baud rate increases, the timing margin available for sampling decreases. Under these conditions, increased clock phase noise can cause the eye pattern to close at the receiver, making it more difficult to distinguish between “0” and “1.” If clock-signal fluctuations occur in this state, the sampling point may shift , increasing the probability of bit errors.
As requirements for phase noise and jitter become stricter with higher speeds, clock performance becomes a critical factor in communication stability. Phase jitter is not simply waveform distortion. It is a key performance indicator that supports signal integrity itself.
Ultra-Low-Jitter Clocks Are Critical for Optical Communication, SerDes, and DSPs
In optical communication modules, SerDes, and DSPs, clock performance has a direct impact on overall system performance . Clocks provide the timing reference that underpins transmit and receive synchronization accuracy as well as signal quality, making ultra-low-jitter performance increasingly important.
In optical communication modules, timing deviation between transmission and reception can degrade signal integrity . Because SerDes handles high-speed serial transmission, the phase noise of the input clock is a key factor influencing performance. Clock instability can impair signal integrity and contribute to transmission degradation across the PCB. In DSPs, reduced synchronization accuracy lowers the precision of correction processing, preventing the device from fully achieving its intended performance.
The same applies to GPU clusters. If communication timing and processing timing become misaligned, waiting time and communication latency may increase. In the 1.6T era, clocks are no longer merely peripheral components; they are a foundational technology that supports the reliability and performance of the entire system.
Clock Design Challenges in the High-Speed Optical Communication Era
In high-speed optical communication, PLL-based configurations have been widely adopted to generate stable high-frequency clocks. At the same time, as communication speeds increase, requirements for phase noise and jitter are becoming increasingly stringent.
In the past, high-frequency clock generation using PLLs was sufficient for many applications. However, as communication speeds transition from 800G to 1.6T-class systems, demands on clock performance are also increasing. As a result, not only PLL design itself but also minimizing noise at the clock source has become an important design consideration.
This section examines key clock design challenges in high-speed optical communication.
PLL Configurations Have Long Been Common for High-Frequency Clock Generation
For many years, PLLs ( phase-locked loops) have been widely used to generate high-frequency clocks. A PLL synchronizes an oscillator with a reference clock, making it possible to generate a high-frequency clock from a relatively low-frequency reference signal.
A PLL typically consists of a phase detector, a low-pass filter, and a VCO (voltage-controlled oscillator). These components stabilize the phase and frequency of the output signal. For this reason, PLLs have been adopted in many high-speed communication systems, including optical communication equipment, network equipment, and SerDes.
From the pre-800G era to the present, PLLs have continued to play a vital role in high-speed communication systems. However, as communication speeds increase, requirements for clock performance are becoming stricter year by year. In addition to stable high-frequency clock generation, low jitter and low phase noise have become important design requirements.
Noise Countermeasures During Clock Generation Become Critical in High-Speed Communication
As communication speeds increase, noise introduced during clock generation can no longer be ignored. Phase noise and jitter directly affect signal integrity , making noise countermeasures an important design theme in high-speed communication systems.
In a typical PLL configuration, the process of frequency multiplication itself can amplify noise, creating the risk of jitter accumulation. To suppress this noise, designers may incorporate additional circuitry such as jitter cleaners. However, this approach involves trade-offs, including increased component count, larger PCB area, higher power consumption, and greater heat generation.
MEMS oscillators and PLL-based oscillators may exhibit excellent standalone performance. However, when mounted near communication ICs, they can be affected by factors such as power-supply noise and thermal conditions, making it more difficult to maintain their expected performance.
In AI data centers, high-density integration and elevated operating temperatures are becoming increasingly common. Therefore, evaluation must consider not only the standalone performance of the oscillator, but also whether stable clock performance can be maintained at the system level.
Clock Performance Requirements Are Becoming Even Stricter in AI Data Centers
In AI data centers, requirements for clock performance are becoming stricter than ever. In 800G and 1.6T-class optical communication systems, per-lane transmission speeds continue to increase, significantly reducing the timing margin available for signal sampling and decision-making.
When timing margin decreases, even slight phase jitter can degrade BER. In addition, densely integrated optical modules are more susceptible to heat and noise. To maintain communication reach and transmission quality, adding noise-suppression circuits can be difficult due to space and thermal constraints. As a result, reducing noise at the clock source itself is becoming an increasingly important design strategy.
In fact, products for high-speed optical communication that support operation at +105°C have already been introduced . In the 1.6T era, clock design requires a comprehensive approach that considers not only frequency performance, but also low jitter, thermal stability, and real-world operating conditions.
PLL-Free Fundamental-Mode Oscillation as an Approach to Ultra-Low Jitter
In high-speed optical communication systems beyond 1.6T, requirements for clock performance continue to increase. While conventional PLL-based designs remain widely used, there is growing interest in new approaches that reduce noise at the clock source itself.
One such approach is PLL-free fundamental-mode oscillation, which directly generates high frequencies without using PLLs or frequency multiplier circuits. This section explains its technical features and advantages.
What Is PLL-Free Fundamental-Mode Oscillation?
PLL-free fundamental-mode oscillation is a method of directly generating a high-frequency signal from a crystal without using PLLs or frequency multiplier circuits. Because the clock generation path can be simplified, potential noise sources can be reduced.
In conventional high-frequency clock generation, frequency conversion using a PLL is widely employed. However, configurations that involve frequency conversion can introduce phase noise and jitter, and their impact becomes increasingly significant as communication speeds increase. In 1.6T-class high-speed optical communication, even small amounts of jitter can affect signal integrity , making low noise at the clock source itself a critical design challenge.
Fundamental-mode oscillation directly generates high frequencies, making it easier to suppress harmonic components and obtain a clock with high signal purity. In high-speed optical communication, where ultra-low jitter is required, this approach is attracting attention as a promising way to improve the quality of the clock source itself.
Why PLL-Free Configurations Are Attracting Attention in High-Speed Optical Communication
One of the primary reasons PLL-free configurations are attracting attention is their ability to simplify the clock-generation path. The more complex a circuit becomes, the greater the possibility that noise will be introduced.
In 1.6T optical communication, requirements for phase noise and jitter are more stringent than ever. As communication speeds increase, the timing margin available for signal decisions decreases, making even small amounts of clock jitter difficult to ignore. As a result, there is growing interest in approaches that generate high-purity clocks while minimizing the use of frequency conversion circuits.
| Comparison Item | PLL Configuration | PLL-Free Fundamental-Mode Oscillation |
|---|---|---|
| High-frequency generation | Performs frequency conversion | Directly oscillates at the fundamental mode |
| Circuit configuration | Tends to be complex | Simple |
| Signal purity | Noise countermeasures are important | Easier to improve |
With PLL-free configurations based on fundamental-mode oscillation, higher signal purity can be achieved by minimizing the generation of unwanted harmonic components. In AI data centers and optical transceivers where high-density integration is advancing, this approach is attracting attention as an important technology for maintaining communication performance.
High-Frequency Fundamental-Mode Oscillation Enabled by KoT cut® and OPAW® Technologies
PLL-free fundamental-mode oscillation is an attractive approach, but directly oscillating at high frequencies in the fundamental mode requires advanced technology on the crystal device side. At the core of this approach are River Eletec’s proprietary KoT cut® and OPAW® technologies. Both are patented technologies developed by the company to achieve both high frequency and low phase noise.
KoT cut® is a technology that optimizes the crystal cut angle. In high-frequency applications, where crystal elements must be manufactured extremely thin, maintaining mechanical strength has historically been a significant challenge. KoT cut® overcomes this physical limitation and enables high-frequency fundamental-mode oscillation in the 500 MHz to 1000 MHz range. By combining this technology with OPAW®, which supports both high-frequency operation and low-noise performance, River Eletec has achieved excellent frequency stability and phase-noise characteristics. In SPXO devices, RMS phase jitter can be as low as 5 femtoseconds (fs).
KoT cut® and OPAW® technologies are expected to find applications in fields requiring both high frequency and high precision, including 5G and 6G communication equipment, optical communication modules, ADCs, DACs, and test and measurement equipment. They can be considered a key technology platform for next-generation communication fields that demand both high frequency and low phase noise, including clocks for optical transceivers and DSPs in AI data centers.
KCRO-05: Enabling PLL-Free Fundamental-Mode Oscillation
River Eletec’s KCRO-05 is a crystal oscillator that embodies the PLL-free fundamental-mode oscillation described in the previous section. Leveraging the company’s proprietary technologies, it achieves direct oscillation at 625 MHz without the use of a PLL. As an ultra-low-phase-noise crystal oscillator, it delivers world-class low-jitter performance, with a typical RMS phase jitter of just 12 fs.
This section introduces the key technical features and advantages of the KCRO-05.
What Is KCRO-05?
KCRO-05 is an ultra-low phase-noise crystal oscillator developed by River Eletec for optical transceiver applications in AI data centers. The integrated IC has also been specifically designed to meet the ultra-low-jitter requirements of 1.6T-class high-speed optical communication systems.
Its key feature is the use of River Eletec’s proprietary KoT cut® and OPAW® technologies to achieve direct oscillation at 625 MHz without the use of a PLL. While conventional high-frequency clock generation typically relies on PLLs, the KCRO-05 delivers a high-purity clock signal through fundamental-mode oscillation.
With a typical RMS phase jitter of just 12 fs, the KCRO-05 offers world-class low-jitter performance and is designed to meet the demanding requirements of high-speed optical communication systems and AI data center equipment. It is positioned as one of River Eletec’s core products for the next-generation optical communication market.
High-Frequency Clock Technology Supporting 625 MHz Fundamental-Mode Oscillation
KCRO-05 is a high-frequency clock solution that achieves 625 MHz fundamental-mode oscillation. Its primary advantage is its ability to combine the low-jitter performance and high-frequency operation required for next-generation optical communication systems.
In optical transceivers for AI data centers, increasing communication speeds demand clock signals with exceptionally high signal purity. By generating high-frequency signals without relying on a PLL, KCRO-05 reduces potential noise sources associated with frequency conversion and delivers a highly stable, low-jitter clock output.
In addition to excellent jitter performance, with a typical RMS phase jitter of 12 fs and a maximum of 20 fs, the product supports a wide operating temperature range of -55°C to +105°C. Even in AI data centers where high-density integration and elevated operating temperatures are common , this specification is designed to help ensure stable phase-noise performance under elevated temperatures and maintain synchronization accuracy across the system over the long term.
Features as a Clock Solution for High-Speed Optical Communication
KCRO-05 is a clock solution optimized for high-speed optical communication. In addition to its ultra-low-jitter performance, it has been designed with compact size and ease of integration in mind.
First, its PLL-free configuration enables a high-purity clock signal , supporting high-speed data transfer and high-precision signal processing. In addition, it reduces the mounting area by approximately 40% compared with a standard 3225-size product, making it suitable for optical module designs where higher density is required.
In 1.6T optical communication modules, high performance and low power consumption must be achieved within increasingly limited space. By combining low-noise operation through fundamental-mode oscillation with a compact form factor, KCRO-05 offers a compelling solution for next-generation high-speed communication infrastructure, including optical transceivers and DSP clocking applications in AI data centers.
Three Advanced Applications Where KCRO-05 Demonstrates Its Value
Ultra-low-jitter clocks play an important role in systems that require high communication performance and precise synchronization. In particular, clock performance is directly linked to overall system performance in 1.6T optical transceivers, AI servers, and high-density optical modules.
The following sections explain the key application areas for KCRO-05.
1.6T Optical Transceivers
KCRO-05 is well suited for use as a clock source in 1.6T optical transceivers. In ultra-high-speed transmission systems operating at approximately 200 Gbps per lane, even small amounts of jitter can affect communication performance.
Next-generation form factors such as OSFP-XD require both high-density integration and increased transmission capacity. To fully realize the performance of DSPs and SerDes that process optical and electrical signals, a high-purity reference clock is essential. Clock jitter can degrade BER performance across the entire communication path.
As the standardization and deployment of 1.6T optical communication systems continue to advance, the importance of ultra-low-jitter clock devices will only increase. KCRO-05 represents a compelling solution capable of meeting these demanding requirements.
AI Servers and GPU Clusters
As generative AI continues to gain widespread adoption, GPU clusters are growing in scale, resulting in a significant increase in server-to-server communication. As a result, maintaining highly accurate clock synchronization within AI servers has become an important factor in overall system efficiency and stability.
In environments where GPUs exchange large volumes of data at high speed, precise alignment between communication timing and processing timing is critical. The stable fundamental-mode oscillation of the KCRO-05 can help improve synchronization accuracy across the system and minimize latency associated with timing mismatches and communication delays. This can contribute to improved AI training efficiency and, ultimately, lower operating costs in large-scale deployments.
High-Density Optical Modules
In high-density optical modules, achieving both clock performance and integration efficiency is also important. As communication speeds increase, more functions must be integrated into increasingly limited mounting space.
In optical modules equipped with high-speed SerDes, clock jitter directly affects signal integrity . In addition, high-density mounting environments are more susceptible to heat and power-supply noise, requiring high stability from the clock device. To maintain signal integrity, designers must consider not only low-jitter performance, but also package size, mounting density, and thermal stability.
KCRO-05 combines a compact form factor with ultra-low-jitter performance, making it well suited for 800G and 1.6T-class optical modules, where integration density continues to increase. It also has the potential to support future co-packaged optics (CPO) architectures that integrate ASICs and optical modules, where even greater space constraints and more challenging thermal environments are expected. As a clock solution for next-generation optical communication infrastructure, KCRO-05 represents a noteworthy option.
Conclusion: Clock Design Approaches Will Become Increasingly Important in the 1.6T Era
AI data centers are transitioning from 800G to 1.6T-class communication speeds, driving increasingly stringent requirements for phase jitter and phase noise. As a result, clock design has become more important than ever for maintaining communication performance.
One approach attracting growing attention is PLL-free fundamental-mode oscillation, which seeks to reduce noise at the clock source itself. River Eletec’s KCRO-05 leverages the company’s proprietary KoT cut® and OPAW® technologies to achieve 625 MHz fundamental-mode oscillation and ultra-low-jitter performance, with a typical RMS phase jitter of just 12 fs.
As next-generation high-speed communication infrastructure continues to evolve—including 1.6T optical transceivers, AI servers, and high-density optical modules—design approaches that consider not only frequency performance but also clock-source performance will become increasingly important. Among these approaches, PLL-free fundamental-mode oscillation is expected to attract even greater attention as a promising solution for future high-speed communication systems.
